1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to an input circuit that receives a signal from the outside and transmits the received signal to an internal circuit.
2. Related Art
A semiconductor integrated circuit includes a signal transmitting unit that receives a signal and transmits it, and a signal processing unit that processes the signal transmitted by the signal transmitting unit according to a predetermined operation. The signal processing unit is generally called a core circuit of the semiconductor integrated circuit. In this core circuit, a large number of elements are integrated within an allowable range of design and process technologies of the semiconductor integrated circuit. The signal transmitting unit includes an input circuit and an output circuit disposed therein. The input circuit transmits a signal transmitted from the outside to the signal processing unit inside the semiconductor integrated circuit, and the output circuit outputs data transmitted by the signal processing unit to the outside.
Among semiconductor integrated circuits, in the case of a semiconductor memory, an input circuit mainly receives an address signal or data so as to transmit it to a memory core region inside the semiconductor memory, and an output circuit outputs a data signal corresponding to an input address to the outside of the memory.
As such, the input circuit receives a data signal or an address signal transmitted from outside of the input circuit and transmits it to an inner part of the semiconductor integrated circuit. The input circuit needs to perform an accurate buffering operation such that the semiconductor integrated circuit operates reliable.
FIG. 1 is a circuit diagram illustrating an input circuit for a semiconductor integrated circuit according to the related art. The input circuit according to the related art is generally implemented by a differential amplifier.
Referring to FIG. 1, the input circuit for a semiconductor integrated circuit according to the related art includes a MOS transistor Q1 that receives a reference voltage vref, a MOS transistor Q2 that receives an input signal in from the outside, two MOS transistors Q3 and Q4 that form a current mirror, two MOS transistors Q5 and Q6 for pull up that are enabled or disabled according to an enable signal enable, and a MOS transistor Q7 that receives the enable signal enable and drives differential amplifying operations of the two MOS transistors Q1 and Q2. The input circuit for a semiconductor integrated circuit further includes, as an output terminal, an inverter I1 that inverts a signal provided by a common node between the MOS transistors Q2 and Q4 and outputs an output signal out. Also, the input circuit of FIG. 1 uses a power supply voltage vdd and a ground voltage VSS as source voltages. The MOS transistors Q1 and Q2 operate as input transistors, the MOS transistors Q3, Q4, Q5, and Q6 operate as pull-up transistors, the MOS transistor Q7 operates as a driving transistor, and the inverter I1 operates as an output driver.
First, if the enable signal enable is input in a state where the enable signal enable is activated, that is, the enable signal enable becomes a high level, the MOS transistors Q5 and Q6 become disabled, and the MOS transistor Q7 becomes enabled, which provides a bias current of the MOS transistors Q1 and Q2.
The reference voltage vref is inputted to the MOS transistor Q1 in a state where it is maintained at a predetermined level. Meanwhile, if the input signal in is inputted to the MOS transistor Q2, the difference between the signals that are supplied from the MOS transistors Q3 and Q4 forming a current mirror to the two MOS transistors Q1 and Q2 is generated, due to the difference between the input signal in and the reference voltage vref. At this time, a signal that corresponds to the difference between the signals is transmitted to the input of the inverter I1. The inverter I1 inverts the input signal according to the size of the signal transmitted to the input of the inverter I1, and outputs an output signal out. For example, when the input signal in is inputted at a signal level higher than the reference voltage vref, a turned-on period of the MOS transistor Q2 is longer than that of the MOS transistor Q1, and a large amount of current flows through the MOS transistor Q2. As a result, the inverter I1 generates an output signal of a high level. In contrast, when the input signal in is inputted at a signal level lower than the reference voltage vref, the turned-on period of the MOS transistor Q2 is shorter than that of the MOS transistor Q1, and a small amount of current flows through the MOS transistor Q2. As a result, the inverter I1 generates an output signal of a low level.
Meanwhile, during a manufacturing process of the semiconductor integrated circuit, as a MOS transistor is manufactured according to process conditions, characteristics of the MOS transistor gradually varies. Also, a voltage level of the power supply voltage vdd can vary gradually with respect to the environment where the semiconductor integrated circuit operates. The operational characteristics of the MOS transistor that forms the input circuit also varies gradually according to an ambient temperature at the time of operation.
That is, the operational characteristics of all MOS transistors that form an input circuit also vary due to the variation in PVT (process, voltage, and temperature). As a result, even when a duty ratio of the input signal in inputted to the input circuit is constant, it varies while passing through the input circuit, and a duty ratio is distorted in an output signal out of the input circuit.
The input circuit is designed to have a structure in which even when an input signal input having a predetermined duty ratio becomes an output signal, the input signal is outputted with the predetermined duty ratio. However, as described above, the operational characteristic of the input circuit continuously varies according to the PVT, and when the input signal becomes the output signal out, the duty ratio is distorted. When the duty ratio is distorted, a margin of a setup/hold time is also reduced.
The setup/hold time refers to a margin in which the semiconductor integrated circuit can receive a desired signal according to a timing of a rising edge or a falling edge of a clock signal. When the duty ratio is distorted, the margin of the setup/hold time is reduced, and signals to be inputted to the semiconductor integrated circuit may not be securely inputted, which causes an erroneous operation.